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A digital filter structure requiring only m-bit delays, shifters, inverters, and m-bit adders plus simple logic circuitry

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2 Author(s)

digital filter structure is presented which requires only m -bit adders, shifters, and inverters, where m is the state-variable word length, to exactly realize the arithmetic operations for state equations. It is assumed that the coefficients in the state equations are finite-wordlength binary numbers; the canonical signed digit code is used to simplify these coefficients. All bits (including underflow bits) of the next state variables are computed, using two's complement (2's C) arithmetic, so the only source of roundoff error is the truncation of the exact next-state variables to m bits. Simple logic circuitry produces magnitude truncation, which suppresses all zero-input limit cycles if a diagonal Lyapunov function exists. Thus the above structure is applied to state equations derived for wave digital filters, which possess a diagonal Lyapunov function and yield short coefficient word lengths due to low sensitivity properties. A computer-simulated example, a third-order elliptic low-pass filter, is given with unit-sample response and frequency response for m equal to 8 and 16 bits.

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Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 10 )