Skip to Main Content
Digital automatic test generation has been successful due to simplified modeling at the logic gate or higher level, rather than the component level, and to logic simulation performed for the stuck-at failure mode only. Analog automatic test generation generally requires modeling and simulation at the component level and continuous failure modes over a certain range of parameter values. As a result, most analog automatic test generation and fault isolation techniques demand a large computational capability on the ATE or off-line computers. Any practical analog automatic test generation solution must eventually address this problem. All analog automatic test generation techniques presently under investigation assume the availability of all or certain designated nodes as test points for stimulus injection and/or response measurement. This assumption suggests the possibility of GO-NO-GO tests to fault isolate to a "primitive," which may contain several circuit components. The "complementary signal" design suggested by Schrelher, appears well suited for providing an effective GO-NO-GO test; the signal and its response are determined by the poles and zeros of the circuit.