Mappings and algorithms for gate modeling in a digital simulation environment

It is obvious that there are different degrees of approximation to the signal values in digital circuits. The more signal states we use in digital simulation, the more information we can expect from the simulated result. On the other hand, the cost to design and implement a digital simulator will increase substantially as the number of states increases. Also, it takes more computer time to complete a simulation run in this case. Consequently one of the major tasks in designing a digital simulator is to select the proper number of signal values. It is usually adequate to use a five-value signal model in design verification and a three-value signal model in fault simulation. A complete analysis of these two models is presented in this paper. In addition, formal mathematical mappings and algorithms are synthesized for these models.