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An improved successive-approximation register design for use in A/D converters

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1 Author(s)

An improved design for a successive-approximation register (SAR) for use in A/D converters is presented. Thne proposed design is suitable for I^{2}L implementation such that a definite savings in devices is obtained over previous designs using the separate sequencer and code register approach. This particular design scheme operates in a fully synchronous mode with the clock allowing a reduction in propagation delay to be realized.

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Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 7 )