By Topic

Optimum LSI implementation for a digital phase-locked loop

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

A logically selective delay of a parallel output shift register can phase lock the input/output waveforms. The calculated precision of the phase-lock is related to the shift register's bit size and clock and input frequencies. This basic idea is extended to multistage (or multilevel) operations. For optimum LSI implementation, a technique is described which minimizes bit size and the delay function logic circuitry for a given precision. The method proves that for high-precision operations the shift register's bit size and the delay selecting logic circuitry are reduced, thus improving operating efficiency. Also discussed is the design tradeoff between level complexity and circuit size. Finally, extension to synchronization application is considered.

Published in:

Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 4 )