Three-layer 1.3 µm In1-xGaxAsyP1-ylasers with quaternary confining layers

Improvements in the surface morphology of InGaAsP DH wafers were obtained with addition of small amounts of Ga and As in the confining layers. This method was used to improve interface flatness between active and confining layers, consequently improving wafer yield and reproducibility. Three-dimensional lattice-mismatch data of the confining layers were determined in detail using simultaneous multiple Bragg diffraction of X-rays. In all wafers tested, independent of the active layer thickness, the maximum threshold current density J
th
was at most 60 percent higher than J
th
minimum. The minimum normalized threshold current density obtained by us-3.4 kA/cm
²
μmis to our knowledge the lowest reported to date. Low resistance contacts-differential series resistance of 1 to 2 Ω for 10 μm SiO
2
stripe-geometry contact-can consistently be directly applied to tile top confining layer, thus dispensing with file need of a cap layer. CW operation at room temperature has been achieved with these three-layer devices.