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Single chip decoder design for large numeric displays

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1 Author(s)
A. Noore ; Dept. of Electr. & Comput. Eng., West Virginia Univ., WV, USA

The author describes an integrated decoder design for displaying large English numeric digits using four clusters of standard seven-segment displays. The viewing area for each digit in the proposed design is four times the size of a standard display. It is also shown that the net power consumed by displaying any numeric digit using the proposed four-cluster display layout is less than that consumed by a single seven-segment display

Published in:

IEEE Transactions on Consumer Electronics  (Volume:37 ,  Issue: 4 )