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Real-time implementation of the VSELP on a 16-bit DSP chip

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2 Author(s)
Myung H.Sunwoo ; Motorola Inc., Austin, TX, USA ; Park, S.

A description is given of a real-time implementation of the vector sum-excited linear predictive (VSELP) speech coder, which has been chosen as the digital cellular standard in North America and Japan. This real-time implementation of the VSELP algorithm is realized using a 16-bit general-purpose digital signal processor (GPDSP) with an onchip codec. The principles of the VSELP algorithm and the real-time implementation of the algorithm on the GPDSP chip are addressed. Also discussed are the finite word length effects and possible methods to reduce the effects

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:37 ,  Issue: 4 )

Date of Publication:

Nov 1991

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