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An 80-NS NDRO ferrite core memory design

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4 Author(s)
Bosch, L. ; IBM Corporation, Poughkeepsie, N.Y. ; Flaker, R. ; Hottenrott, H. ; Lockhart, N.

The use of fast-rising short-duration pulses in the design of a 1K - 144 bit NDRO memory with permeability sensing leads to high-frequency considerations not normally encountered in ferrite core memories. In particular, the high-frequency character of the device must be recognized to properly evaluate cycle time capabilities and array transmission. The design of this memory centers around a 2-core-per-bit word-organized array. The array was optimized with the aid of a computer analysis that considered the device, array geometry, and line termination as variables. The performance of this system has been tested by a cross-section model incorporating full length, fully populated word and digit lines.

Published in:

Magnetics, IEEE Transactions on  (Volume:3 ,  Issue: 3 )

Date of Publication:

September 1967

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