By Topic

Design of half-million bit wire memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
J. Kefalas ; Electronic Data Processing Division, Honeywell, Inc., Waltham, Mass

A high volumetric density wire memory stack of 12 000 bits/in3was designed. The high bit density was obtained by the introduction of a novel and continuous digit line printed circuit which is also used to separate and support the plated wires. The printed circuit is also used for interconnecting the planes of the memory stack. Analysis of digit current and signal coupling is given. The advantages of the proposed memory stack configuration are apparent. These include low digit current and digit signal coupling along with good word and digit noise cancellations and high bit density.

Published in:

IEEE Transactions on Magnetics  (Volume:3 ,  Issue: 2 )