Design of half-million bit wire memory

A high volumetric density wire memory stack of 12 000 bits/in
³
was designed. The high bit density was obtained by the introduction of a novel and continuous digit line printed circuit which is also used to separate and support the plated wires. The printed circuit is also used for interconnecting the planes of the memory stack. Analysis of digit current and signal coupling is given. The advantages of the proposed memory stack configuration are apparent. These include low digit current and digit signal coupling along with good word and digit noise cancellations and high bit density.