By Topic

Low crosstalk packaging design for Josephson logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Aoki, Katsuhiko ; NTT Opto-electronics Laboratories, Tokyo, Japan ; Tazoh, Y. ; Yoshikiyo, Haruo

Theoretical and experimental studies are accomplished for inductive crosstalk noise reductions at Josephson chip-to-card connectors. This noise is induced by large AC power and high switching speed signal currents. The crosstalk mechanism was analyzed using a Partial Element Equivalent Circuits Model. Ground inductance causes not only crosstalk noise between connectors but also ground fluctuation noise inside the chip. This ground noise is large enough to cause false logic operations. Test chips and cards with improved connectors were produced for an experimental evaluation. Power crosstalk noise was measured using Josephson sampling circuits fabricated on the chip. The crosstalk noise - signal level ratio was less than 2.5%, when 250 MHz, 50 mA power currents were supplied. Crosstalk noise between neighboring signal connectors was also reduced to negligible level, including the worst case. These results favorably agree with calculations. This low crosstalk packaging design can be applied to high speed Josephson logic systems.

Published in:

Magnetics, IEEE Transactions on  (Volume:21 ,  Issue: 2 )