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An integration of all refractory Josephson logic LSI circuit

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9 Author(s)
S. Kosaka ; Electrochemical Laboratory, Umezono, Sakura-mura, Niihari-gun, Ibaraki, Japan ; A. Shoji ; M. Aoyagi ; F. Shinoki
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An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.

Published in:

IEEE Transactions on Magnetics  (Volume:21 ,  Issue: 2 )