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A high-performance bubble memory chip

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4 Author(s)
Lung-jo Tao ; IBM Corporation, San Jose, California ; A. Desouches ; D. Hannon ; R. Holmes

The design and the experimental results of a bubble memory chip with permalloy propagation elements are described. High data rate, short access time, and data integrity are achieved by architectural design rather than by using Complex bubble devices. Emphasis is placed on the use of simple low-current wide-margin switches to allow for time multiplexing and to reduce packaging costs. The square chip consists of two half chips of long major/short minor loop design. The minor loops are divided into miniblocks to further improve access time. The minor loops are connected to the output channel by transfer-out switches. Data integrity is achieved by using a passive replicator in a reentrant loop. Update of the data is accomplished by swapping data between the reentrant loop and the data channel with a pair of switches operated in series mode. The reentrant loop is connected to the minor loops by transfer-in switches. The data switch and the thin-film detector of the two half chips are rotated 180° with respect to each other and are time multiplexed. An overall bias margin of 20 to 30 Oe was obtained at 250 kHz with a sinusoidal drive field of 50 to 60 Oe at 40°C on chips with free bubble collapse bias of about 200 Oe.

Published in:

IEEE Transactions on Magnetics  (Volume:19 ,  Issue: 5 )