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The design and characterization of a 1-Mbit block-replicate (swap) chip organized as 584 loops of 2048 bits each is described. Double period propagation elements are employed in both input and output tracks. All propagation elements employed outside of the storage area have a period in excess of 14 μm to minimize step coverage and conductor induced stress problems. A semi-planar polyimide based process is used to fabricate the chips. The replicate gate is subdivided to reduce the voltage requirements. By using copper conductors and simple voltage boosting techniques, the chip can be operated from a 12-V supply. The swap gate is a slight modification of an existing double period design and the replicate gate is based upon a modification of Bonyhard's sideways replicator design. A half-shorted (backside) chevron stretcher detector is employed. Operating characteristics of these components are given over temperature for both chip and package testing. Two programmable map loops are included on-chip to enhance yield, either one of which may be loaded by selecting the transfer-in pulse parity with respect to an alternate bit data stream. The write pulses are multiplexed on the same control line as the map loop read pulses thus saving pins. The design details and the operating margins for the map loops are given.