Skip to Main Content
Josephson latching logic devices can be powered by a bipolar trapezoidal waveform shaped from a incoming ac by a voltage regulator consisting of two or four Josephson junctions in series. For reasons of local power regulation, uniform thermal loading and timing, it is desirable that there be a number or regulators (typically 16-64) distributed over the surface of the chip. These regulators are driven in parallel by a symmetric tree-like distribution network with one or more inputs at the chip periphery. Provided all regulators and their loads are identical, the regulated power waveform will be the same everywhere on the chip. We have used a Josephson sampling oscilloscope to study the effects of asymmetry in a simple power system with two regulators at frequencies up to 500 MHz (representing a 1ns logic cycle time). Initially the nearly identical voltage waveforms across the two regulators are measured with a common time base using high resolution on-chip sampling techniques. The resistive load across one of the regulators is then mechanically changed by a factor of two or three. The subsequently measured waveforms are somewhat different in shape and displaced from each other by approximately 100 ps. This experiment and accompanying simulations help established design limits on acceptable levels of asymmetry in the on-chip power distribution system.
Date of Publication: Jan 1981