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Implementing a bubble memory hierarchy system

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2 Author(s)
R. Segura ; NASA-Langley Research Center, Hampton, VA ; C. Nichols

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Published in:

IEEE Transactions on Magnetics  (Volume:15 ,  Issue: 6 )