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A micro-processor interfaced 1 MBIT bubble memory

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10 Author(s)
Yoshizawa, S. ; Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan ; Sugie, M. ; Kita, Y. ; Yamaguchi, N.
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Compact solid-state read-write memories with non-volatility are much desired for micro-processor applications. 1) Recently, we have realized a very compact and convenient 1Mbit bubble memory board, using newly developed controller LSI (BMC: Bubble Memory Controller) and high density 256 kbit bubble memory chips (8μ period). The memory board is only 18cm × 15cm size and activated by a single power source of +5V. An outstanding feature of this memory is a perfect protection of memory contents against power supply accidents (+5V, open or short) . This protection is realized using a new method by BMC and a peripheral circuit on the board. Another feature is a new automatic handling of defect loops in the bubble memory chips. A defect loop map is stored in the special page address of bubble chip itself and BMC reads this map and stores it into an internal RAM of BMC, when power switch is turned on. Using this information, BMC masks the defect loop automatically. The compactness of this board originates from the realization of BMC-LSI ( n-Mos ) . BMC contains about 15k transistors and controls the bubble chip using the data of 6 kbit internal ROM. Present memory can be connected directly to bus lines of micro-processor 6800 series and 8080 series. A 256 kbit bubble chip employs a block-replicator and even-odd organization and is composed of 280 minor loops with 1135 positions. Its high density (8μ period) was achieved by the introduction of a new planer process using PIQ resins. The performances of this memory board will be described.

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Magnetics, IEEE Transactions on  (Volume:15 ,  Issue: 6 )