By Topic

Memory organization using imperfect bubble chips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
H. Murakami ; Nippon Electric Company Ltd., Kawasaki, Japan.

A method is presented for using imperfect bubble chips having a major/minor loop scheme. The imperfect chips are allocated in a memory module in such a manner that defective minor loop groups are arranged in a predetermined regular relationship with respect to the positions of the defective groups within the chips. A statistical analysis is presented to determine the value of chip yield under the condition that existense of one or more defective groups within a chip are permissible. A memory system cost reduction of up to 50 percent is demonstrated for the fault-tolerant scheme chosen as an example, since the addition of the electronic circuit which enables the use of the imperfect chips is very simple.

Published in:

IEEE Transactions on Magnetics  (Volume:13 ,  Issue: 5 )