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A hybrid bubble organization is proposed which combines the advantages of both major-minor loop and decoder organizations while eliminating some of the complexity of the decoder organization. The organization consists of multiplexed decoder sections in which the selection of different blocks is performed in part by decoding and in part by a major-minor type time domain selection. The number of decoder steps can be reduced at the expense of a modest increase in access time. This organization allows the use of a low current retarding type decoder element, thus reducing the on-chip power consumption. Also, a number of decoder conductors can share the same driver, reducing the number of external chip connections.