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A fast-access, non-volatile memory system using 3- μm bubble 80-kbit chips has been designed for an experimental model and evaluated from a systems viewpoint. The goal of this project is to investigate from both the side of technology and cost if the memories built with major-minor organized 3 μm bubble chips are acceptable in the commercial market. This paper describes the practical design of a bubble memory system, with a capacity of 8-Mbits and an average access time of approximately 1 ms at drive frequencies of up to 500 kHz, which involves memory system organization, redundancy design using chips with excess minor loops, packaging, electronic circuits scheme and other considerations. The results of the experiment and the system cost estimate based on this design are also described.