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Error-correcting codes for byte-organized memory systems

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1 Author(s)

Techniques are presented for the construction of error-correcting codes for semiconductor memory subsystems that are organized in a multibit-per-chip manner. These codes are capable of correcting all single-byte errors and detecting all double-byte errors, where a byte represents the number of bits that are fed from the same chip to the same codeword.

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Information Theory, IEEE Transactions on  (Volume:32 ,  Issue: 2 )