Referenced Items are not available for this document.
Techniques are presented for the construction of error-correcting codes for semiconductor memory subsystems that are organized in a multibit-per-chip manner. These codes are capable of correcting all single-byte errors and detecting all double-byte errors, where a byte represents the number of bits that are fed from the same chip to the same codeword.
Published in:
Information Theory, IEEE Transactions on
(Volume:32
,
Issue:
2
)
Date of Publication: Mar 1986
- Page(s):
- 181 - 185
- ISSN :
- 0018-9448
- Digital Object Identifier :
- 10.1109/TIT.1986.1057171
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Mar 1986
- Sponsored by :
- IEEE Information Theory Society
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