By Topic

Block codes capable of correcting both additive and timing errors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

Binary block codes are constructed that are capable of correcting successive timing errors such as the deletion or insertion of s bits (s\leq D) within a single additive burst of errors of length b or less (b=f+g+2D) , where f and D are the design parameters that specify the length of correctable successive timing errors and g is the length of the correctable additive burst. A decoding algorithm is given and the efficiency of these codes is discussed.

Published in:

IEEE Transactions on Information Theory  (Volume:26 ,  Issue: 4 )