Referenced Items are not available for this document.
Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 μm. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:7
,
Issue:
5
)
Date of Publication: Oct 1972
- Page(s):
- 346 - 351
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1972.1052891
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Oct 1972
- Sponsored by :
- IEEE Solid-State Circuits Society
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