Skip to Main Content
A simple model is derived for the threshold voltage of a MOSFET in a CMOS n-well or p-well process. The model includes the short-channel effects and considers a Gaussian distribution of the n-type implant in the n-well. An expression is derived based on the charge conservation principle for a case of low drain-source voltage V/SUB DS/, which geometrically takes into account the two-dimensional edge effects. The model is in agreement with the measured threshold voltages of typical CMOS (p-channel) transistors. The model is also in agreement with L.D. Yau's model (1974) in the limiting case of uniform channel doping.