A fast 256/spl times/4 CMOS DRAM with a distributed sense and unique restore circuit

A 256 K/spl times/4 CMOS dynamic RAM has been fabricated using a double-poly single-metal n-well CMOS technology with a distributed sense and unique restore (DSR) circuit. The bit line is divided into two segment bit lines, and both n-channel and p-channel latches are connected to each segment bit line in the DSR structure, which provides an improved signal-to-noise ratio and saves the silicon area for decoders and an extra metal layer. The sensing scheme of the distributed sense and unique restore circuit is discussed. The novel bit-line precharge voltage (VPR) generator, which actually holds the VPR at V/SUB cc//2, is described.