Noise-generation analysis and noise-suppression design techniques in megabit DRAMs

A detailed noise-generation model of peak current and voltage-bouncing noise for DRAMs is presented. This model was found to be a very effective tool for predicting and analyzing quantitative bouncing noise level in noise-suppress circuit design, especially for high-performance high-density DRAMs. The resulting performance for the fabricated NMOS 1-Mb DRAM is 100-mA peak current, 6-mA/ns current transition rate, and 0.27-V output voltage-bouncing noise for a standard system board.