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A high-speed 8×8-b parallel array multiplier is developed using sidewall base contact structure (SICOS) technology. The two's-complement multiplication algorithm with carry save adder arrays and carry lookahead adders is utilized. A SICOS transistor results in 14-GHz cutoff frequency and 84-ps/gate ECL switching speed. Multiplication is 2.7 ns with a power dissipation of 900 mW.