By Topic

A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-μm C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0×2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:22 ,  Issue: 2 )