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For pt.II see ibid., vol.SC-21, no.2, p.297 (1986). It is shown that application-specific integrated circuit (ASIC) design schedules are a function of design manpower. There are no significant tradeoffs in managing schedules besides changing the basic design productivity associated with different design methodologies. A quantitative model of the schedule as a function of manpower has been developed based on 81 designs (full custom, cell-based standard cell, and gate-array) from 21 companies. A schedule in weeks equals man-weeks for one-man projects and is proportional to the curve root of man-weeks. Schedules can be reduced by increasing productivity through chip partitioning and, only to a limited extent, through increases in manpower. Increasing productivity through the use of semicustom design methodologies is the most effective method of reducing schedules and costs, since it fundamentally changes the design process.