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A high-performance custom standard-cell CMOS equalizer for telecommunications applications

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4 Author(s)

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:22 ,  Issue: 2 )