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A decoder with OR gates for a Josephson high-density memory circuit

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4 Author(s)

A decoder made of OR gates was designed for a Josephson high-density memory circuit. The advantages of this decoder are its large operating margin and high-speed operation compared with conventional decoders made of AND gates. The decoder was designed for a 16-Kbit random access memory (RAM), and was successfully operated with a delay time of 2 ns.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:22 ,  Issue: 1 )