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13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

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6 Author(s)

The development is discussed for a 13-ns, 500-mW, 16K word×4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:21 ,  Issue: 5 )

Date of Publication:

Oct 1986

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