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A 4-Mbit DRAM with trench-transistor cell

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15 Author(s)

An experimental 5-V-only 1M-word×4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-μm CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 μm/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:21 ,  Issue: 5 )

Date of Publication:

Oct 1986

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