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Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI

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2 Author(s)

The authors describe the synchronous clock distribution problem in VLSI and techniques for its solution. In particular, the advantages and disadvantages of a hierarchical design technique for minimizing clock skew within a VLSI circuit are discussed. In addition, a model for clock distribution networks which considers the effects of distributed interconnect impedances on clock skew is described.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:21 ,  Issue: 2 )