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Realization of quaternary logic circuits by n-channel MOS devices

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6 Author(s)

A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:21 ,  Issue: 1 )

Date of Publication:

Feb 1986

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