Referenced Items are not available for this document.
A 25-ns, 250-mW, 2K/spl times/8 PROM using a 1.2-/spl mu/m n-well CMOS technology is described. Speed and programmability are optimized by separating the READ and WRITE transistor functions in a four-transistor differential cell and using differential design techniques. For the first time, a substrate bias generator is used in an EPROM technology to improve speed and raise latch-up immunity to over 200 mA.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:20
,
Issue:
5
)
Date of Publication: Oct. 1985
- Page(s):
- 964 - 970
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1985.1052422
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Oct. 1985
- Sponsored by :
- IEEE Solid-State Circuits Society
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