Referenced Items are not available for this document.
A 35-ns 8K/spl times/8 CMOS SRAM with address-transition detection design techniques and a novel architecture is described. This design uses a 1.5-/spl mu/m HCMOS twin-well process with polycide gates. A technique for generating internal timing which is impervious to address skew and glitches has been developed. At long cycle times the circuit automatically powers down to a 8-mA active current level with the part selected.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:20
,
Issue:
5
)
Date of Publication: Oct. 1985
- Page(s):
- 941 - 950
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1985.1052419
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Oct. 1985
- Sponsored by :
- IEEE Solid-State Circuits Society
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