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A 35-ns 8K/spl times/8 CMOS SRAM with address-transition detection design techniques and a novel architecture is described. This design uses a 1.5-/spl mu/m HCMOS twin-well process with polycide gates. A technique for generating internal timing which is impervious to address skew and glitches has been developed. At long cycle times the circuit automatically powers down to a 8-mA active current level with the part selected.
Date of Publication: Oct. 1985