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A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 μV equivalent offset voltage and input noise equal to 270 μV. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 μW (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.
Date of Publication: Aug 1985