Cart (Loading....) | Create Account
Close category search window
 

A Design Strategy in CMOS for Microprocessors and Its Application to the Intel 80C48

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

The main purpose in redesigning the 8048 Intel Microcomputer in CMOS technology is to test our tool's efficiency and to evaluate our design methodology, called CAPRI [1], which researches a good factor of regularity. This paper presents a method of implementing microprocessor circuitry in CMOS which uses an ordered stucture of the layout. It allows the designer to work, with a symbolism, on a grid made of polysilicon rows and aluminium columns. Thus, data buses runs in polysilicon lines which seem to give a handicap to this method. Nevertheless, calculations show an acceptable propagation delay time of 46 ns for a 2.5-mm bus (31 ns in the case of an equivalent aluminium bus).

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:20 ,  Issue: 3 )

Date of Publication:

June 1985

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.