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In this paper a 2-/spl mu/m CMOS, microprogrammable Signal Processor Core (SPC) is described,intended as the number crunching unit in single-chip general purpose digital signal processors. This core contains a 16 X 16 bit paralleI multiplier, a 40-bit multiprecision accumulator, a 40--32-bit extractor, an overflow detection unit, a format adjuster, and a three-port register file for local storage of 15 operands. Its 100-ns throughput rate makes it highly suitable for signal processing systems with sample rates up to 50 kHz (speech, telecom, and HiFi audio). The architecture of this unit is discussed in detail.The design approach, using full-custom cells, bit-sliced functional blocks, and a complete bottom-up logical verification of mask data, is also discribed. The Signal Processor Core contains 19 200 transistors on a 15.5-mm/sup 2/ area. This compares with a packing density of 1200 transistors/mm/sup 2/.