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A Full Custom Integrated Circuit for Document Analysis Systems

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3 Author(s)

This paper describes the architecture and design methodology used to produce a new custom IC intended for automatic document analysis. The circuit implements the entire operative part of a dedicated microprogrammed processor for the next generation of page readers which include items such as Optical Character Recognition (OCR) and different codings for graphics and images. The chip provides a wide range of powerful functions, performing up to three operations per cycle. It includes about 10 000 transistor sites and occupies an area of 20 mm/sup 2/. A standard 6-/spl mu/m NMOS technology was used. Typical clock frequency is 2 MHz. The layout was obtained using a highly regular architecture and some automatically generated structures. New CAD tools provided an efficient and short design procedure.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:20 ,  Issue: 3 )

Date of Publication:

June 1985

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