Referenced Items are not available for this document.
The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implemented in both 5- and 3-/spl mu/m CMOS processes.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:20
,
Issue:
2
)
Date of Publication: April 1985
- Page(s):
- 523 - 530
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1985.1052338
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- April 1985
- Sponsored by :
- IEEE Solid-State Circuits Society
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