Referenced Items are not available for this document.
Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:20
,
Issue:
2
)
Date of Publication: Apr 1985
- Page(s):
- 495 - 500
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1985.1052335
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Apr 1985
- Sponsored by :
- IEEE Solid-State Circuits Society
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