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A CMOS line equalizer for a digital subscriber loop

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4 Author(s)

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:19 ,  Issue: 6 )