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A 34000-transistor single-chip floating-point coprocessor fabricated in 3-/spl mu/m double metal NMOS technology is described. The fraction data path, including a shifter and 60-bit carry propagate ALU, is cycled in 100 ns for all operations requiring less than 19 bits of consecutive carry. A versatile carry length detection scheme, which requires minimal additional logic, is used to extend the microcycle for the small percentage of operations in which a long carry exists. Three-bit-per-cycle multiplication and one-and-one-half-bit-per-cycle division algorithms were used to achieve excellent overall performance.
Date of Publication: Oct. 1984