Referenced Items are not available for this document.
Two scaled versions of a 32-bit NMOS reduced-instruction-set computer CPU, called RISC II, have been implemented on two different processing lines using the simple layout rules of C.A. Mead and L.A. Conway (1980). The lambda values are 2 and 1.5 /spl mu/m, corresponding to drawn gate lengths of 4 and 3 /spl mu/m, respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:19
,
Issue:
5
)
Date of Publication: Oct. 1984
- Page(s):
- 682 - 689
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1984.1052208
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Oct. 1984
- Sponsored by :
- IEEE Solid-State Circuits Society
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