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A 70 ns 256K DRAM with bit-line shield

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8 Author(s)

A 256K/spl times/1 dynamic RAM has been developed in a triple-poly, single-metal NMOS technology with a open bit-line architecture. Noncommon-mode noise inherent in the architecture is shielded by a third-level polysilicon plate placed between bit lines and signal lines. The die is 30.2 mm/SUP 2/ and is housed in the standard 300-mil and 16-pin dual-in-line plastic package. The RAM has a worst-case access time of 70 ns. Wire bonding of an extra bonding pad determines whether the RAM is for nibble mode or for page mode; this, it is noted, gives much flexibility to production. Laser repairable redundancy with eight spare columns is implemented for yield enhancement.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:19 ,  Issue: 5 )