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Circuit techniques for a 25 ns 16Kx1 SRAM using address-transition detection

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3 Author(s)

The authors describe special circuit techniques that have been used to produce a 25-ns HMOS 16K/spl times/1 SRAM. In particular, a new dynamic row-decoder driver, hold-valid-data output driver, and column-decoder driver have been developed. A new memory clear function, called the bulk-write feature, that writes all data locations to the same data as the data-in pin in one long (/spl sime/700 ns) write cycle was also developed. This 16K/spl times/1 SRAM has a die area of 25.3K mil/SUP 2/ (16.3 mm/SUP 2/), and was fabricated using a 2-/spl mu/m double-polysilicon NMOS technology.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:19 ,  Issue: 4 )