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The authors describe a novel circuit design for very high-speed bipolar RAMs and the fabrication of: (1) address buffer with varying reference level only at the transient point, (2) memory cell with speed-up capacitor, and (3) sense amplifier with reduced logic stages. A 1K ECL RAM with these new circuits was fabricated using SST-2 (super self-aligned process technology). The access time of this RAM is improved by 50% as against a conventional RAM, and an access time of 1.5 ns is achieved at 0.7 W power dissipation. These results almost coincide with the simulated value obtained using SPICE2.